This invention relates generally to operation of phase-locked loops, and more specifically, to methods and apparatus for loop bandwidth control of phase-locked loops.
Communications standards, such as GR-253-CORE, “SONET Transport Systems: Common Criteria” and GR-1 244-CORE, “Clocks for the Synchronized Network: Common Generic Criteria” specify criteria for the various clocks used in communications equipment for synchronous timing applications. These synchronous timing applications typically use phase-locked loops (PLLs), where a PLL can be an electronic circuit with a voltage or current-driven oscillator that is adjusted to match in phase (and thus lock on) the frequency of an input reference signal. The GR-253-CORE and GR-1244-CORE standards provide MTIE (Maximum Time interval Error) requirements for the cases: after the input reference has been switched, the input reference has changed in frequency or phase, after a holdover. In addition, these standards specify a low bandwidth in order to filter out jitter in the input reference signal. Furthermore, these standards specify a minimum phase error within the MTIE limits.
There are existing methods for controlling operation of PLLs. One existing method uses only two levels of bandwidth, i.e. locked or unlocked. Another existing method requires the capability to measure the instantaneous loop frequency and set the integral loop frequency.
The methods and apparatus described herein helps to achieve the requirements set forth in standards such as GR253-CORE and GR-1244-CORE for stabilizing the phase, after a change in reference or recovery from holdover, within the required time limit, while reducing the jitter associated with a large loop bandwidth change.